Electronic systems may employ a power supply supervisor to indicate when an input power supply voltage is above or below a prescribed threshold. For example, an integrated power-on-reset (POR) device may produce a low logic level at its /RESET output when the input supply voltage is below a prescribed threshold voltage. A high logic level at the /RESET output may be generated when the power supply voltage has been above the threshold level for a defined period of time.
A multi-input power supply supervisor monitors multiple input power supply voltages applied to its respective inputs. It issues a low logic level at its /RESET output when at least one of the input power supply voltages is below the threshold level, and a high logic level when all of the input power supply voltages are above the threshold for a defined period of time.
An output signal produced by a power supply supervisor may be provided to external circuitry. Therefore, logic levels of the output signal must be electrically compatible with the external circuitry. In particular, the designer of a multi-input power supply supervisor often faces the problem of providing an output voltage at a high logic level without knowledge of external circuit characteristics.
A common method used to avoid defining high logic levels in a power supply supervisor is to leave the /RESET output node without an internal “pull-up” structure, i.e. make it an “open-drain” output. Users are required to connect their own “pull-up” devices, such as a resistor, to the output of the supervisor to provide a desired high logic level. However, this method increases system cost and requires larger system area.
Another method used to define a high logic level at the output of the supervisor is to provide a “digital Vcc” pin on the supervisor chip. Users apply a compatible voltage to this pin. The high logic level at the output of the supervisor is pulled up to the voltage defined by the “digital Vcc” pin. However, this method also increases system cost and area.
Also, the designer of a power supply supervisor often faces the problem of specifying power supply order at the supervisor's inputs to maintain compatibility of the power supply supervisor with the applied power supply voltages.
It would be desirable to create a multi-input power supply supervisor that eliminates the need to ascertain the high logic level of an output voltage and to specify the power supply order at its inputs.